Introduction
CorePCIF v4.0
I/O Requirements
Table 6 gives the I/O requirements for CorePCIF. The number of device I/O pins required for the PCI interface varies,
depending on the bus width as well as whether the core supports Target and/or Master functions. The number of
backend device I/O pins that the core requires depends on the core interface. For instance, a device that implements a
PCI-to-serial communication channel may only require a single device I/O pin, whereas a PCI-to-memory interface
may require many I/O pins. Table 6 shows the maximum number of I/O pins, assuming all the core backend pins are
connected to device I/O pins.
Table 6 · CorePCIF I/O Requirements
I/O Count
Core
PCI
Backend
Total
Min. Max. Min. Max.
32-bit Target
64-bit Target
32-bit Master with backend interface
64-bit Master with backend interface
32-bit Target and Master
64-bit Target and Master
32-bit Target and Master with backend interface
64-bit Target and Master with backend interface
48
88
49
88
50
89
50
89
1
1
1
1
1
1
1
1
146
219
162
235
146
219
162
235
49
89
50
89
51
90
51
90
194
307
211
323
196
308
212
324
12
v4.0
相关PDF资料
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相关代理商/技术参数
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